I was looking for a way to pass parameters to Yosys (that would end up in the Verilog source code) at synthesis time.
Posts tagged Cellular Automaton
This is the first post of a series I am writing about designing and running Cellular Automatons in an FPGA. I’ll end up with several variants, from one lighting up LEDs to another one drawing on a VGA monitor. But first, what is a Cellular Automaton?